ESP8266 datasheet(91/117 Pages) ESPRESSIF

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11. UART Introduction

11.4.2. Interface

Open interrupt enable: UART_ENABLE_INTR_MASK(uart_no,ena_mask);

Close interrupt enable:

UART_DISABLE_INTR_MASK (uart_no,disable_mask);

Clear interrupt enable:

UART_CLR_INTR_STATUS_MASK(uart_no,clr_mask);

Get interrupt status UART_GET_INTR_STATUS(uart_no);

11.4.3. Interrupt Type

Receive full interrupt

Interrupt status bits:UART_RXFIFO_FULL_INT_ST

Deﬁnition: When conﬁgure threshold and enable interrupts, triggered will interrupt when rx

ﬁfo data length is greater than the threshold.

Application:more applied in receiving UART data ,cooperating with ﬂow control,dealing with

directly or posting messages or turn into buffer.For example,when the conﬁguration of the

threshold is 100 and the enable full is interruption, the full will interrupt once the serial port

receive 100 Bytes.

Conﬁgure threshold value:

Full interrupt threshold

In the UART_CONF1 register

#deﬁne UART_RXFIFO_FULL_THRHD 0x0000007F //The threshold mask, 7bit long and

range 0 ~ 127

#deﬁne UART_RXFIFO_FULL_THRHD_S 0 //Shift register is 0 (start from 0bit)

Set enable to interrupt:

In UART_INT_ENA register

#deﬁne UART_RXFIFO_FULL_INT_ENA (BIT(0)) //full interrupt enable bit, 1: enable;0:

disable

clear interrupt status:

As for special full interrupts you need ﬁrst to read all ﬁfo received data empty, then write

the clear interruption status register.Otherwise, the interrupt status bit will be set again after

exit.

Please see details in examples of interrupt handling.

Receive overﬂow interrupt

Interrupt status bits:UART_RXFIFO_OVF_INT_ST

Espressif

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2017.05

ESP8266 Scheda tecnica(PDF) 91 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.