Place bypass capacitors

close to power pins.

Place an input resistor close to pin 2

and 6 to minimize stray capacitance.

Place output resistors close

to output pins (pin 1 and 7) to

minimize parasitic capacitance.

Ground and power plane removed from inner layers.

Ground and power plane exist on inner layers.

Place bypass capacitors

close to power pins.

Remove GND and power plane

under pins 1, 2, 7, and 6 to

minimize stray PCB capacitance.

Place feedback resistor on the bottom of

PCB between positive supply pin (8) and

inverting input pins (2, 6).

Noninverting inputs (pin 3 and 5)

terminated in 50

Ÿ.

1

2

3

4

8

7

6

5

A

B

20

OPA2356-EP

SBOS955 – FEBRUARY 2019

www.ti.com

Submit Documentation Feedback

Copyright © 2019, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

Good high-frequency PC board layout techniques should be employed for the OPA2356-EP. Generous use of

ground planes, short direct signal traces, and a suitable bypass capacitor located at the V+ pin assure clean,

stable operation. Large areas of copper also provide a means of dissipating heat that is generated within the

amplifier in normal operation.

Sockets are not recommended for use with any high-speed amplifier.

A 10-µF ceramic bypass capacitor is the minimum recommended value; adding a 1-µF or larger tantalum

capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass

capacitance is essential to achieving very low harmonic and intermodulation distortion.

10.2 Layout Example

Figure 37. Example Layout