EM5049VT datasheet(9/10 Pages) EXCELLIANCE

9 / 10 page

2013/08/30

A.1

EM5049

Functional Description

VO Source/Sink Regulator

The EM5049 integrates a high-performance, high

current linear regulator that is capable of both

sourcing

and

sinking

current.

This

regulator

employs a fast response so that small ceramic

capacitor can be used. To achieve tight regulation

with minimum effect of trace resistance, the FB pin

should be connected to the positive terminal of the

output capacitor.

Reference Input

The output voltage is regulated to track the 1/2

reference voltage at REF pin within

±15mV at all

conditions .

Shutdown Control Function

When EN is driven high, the EM5049 Vo regulator

begins normal operation. When EN is driven low,

VO is discharged to GND through an internal

sinking MOSFET.

POR – Power ON Reset

To let EM5049 start to operation, CNTL voltage

must be higher than its POR voltage even when REF

voltage is pulled higher than enable high voltage.

Typical POR voltage is 3.6V.

Over Current Limit Function

EM5049 features over current limiting function as

well as output short circuit current fold back

function. Typically, before the thermal protection is

triggered, EM5049 can limit its output current to

3.0A (TYP). When output voltage is decreased, the

limiting current level also decreases. When VOUT is

short to GND, or VOUT voltage is zero, the output

current level is limited to 1.5A, typically.

Input and Output Capacitor Selection

For CNTL pin, a 1uF ceramic capacitor is enough for

bypass the supply of CNTL to GND. For VIN pin,

10uF or larger ceramic capacitor is required to

provide bypass path in transient current demand.

VOUT pin is also recommended to have 10uF or

larger ceramic capacitor to be stable and reduce

the VOUT voltage dip when fast loading transient is

happened.

Power Dissipation

The maximum power depends on some conditions,

including of thermal impedance, PCB layout,

airflow,

and

on.

The

maximum

power

dissipation can be calculated by the formula as

below

PD(max)=(TJ(max)-TA) / θJA

TJ(max) is the maximum, junction temperature; θJA is

the thermal impedance from junction to ambient.

The thermal impedance θJA of exposed DFN3X3-10L

is package design and PCB design dependent. The

thermal impedance can be reduced by increasing

the copper area under the exposed pad of the

DFN3X3-10L package. So, to let the copper area as

large as possible is helpful for the thermal

performance of the DFN3X3-10L package.

For recommended specification of EM5049, the

maximum junction temperature is 125 degree C.

The θJA of exposed DFN3X3-10L is 60°C/W on the

standard JEDEC 51-7(4 layers, 2S2P, copper 2 oz)

thermal

test

board.

The

maximum

power

dissipation (at 25°C ambient, on the minimum

exposed pad layout) can be calculated as below:

PD(max at 25°C)=(125°C–25°C)/(60°C/W) = 1.67W

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