HT48RB8 datasheet(13/45 Pages) HOLTEK

13 / 45 page

HT48RB8

Rev. 1.30

February 10, 2003

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets only the PC and SP, leaving the other cir-

cuits in their original state. Some registers remain un-

changed during other reset conditions. Most registers

are reset to the

²initial condition² when the reset condi-

tions are met. By examining the PD and TO flags, the

program can distinguish between different

²chip resets².

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status are shown below.

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Points to the top of the stack

V D D

R E S

Reset circuit

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset timing chart

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