NT5CC64M16GP-DINA datasheet(16/160 Pages) NANYA

Il numero della parte	NT5CC64M16GP-DINA

Spiegazioni elettronici	Commercial, Industrial and AutomotiveDDR3(L) 1 Gb SDRAM

PDF	160 Pages

Scroll/Zoom	100%

Produttore elettronici	NANYA [Nanya Technology Corporation.]

Homepage	http://www.nanya.com

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Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

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DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

tMOD Timing

CKE

MRS

NOP

CMD

ADDR

tMOD

Non

MRS

VAL

Old Setting

Updating Setting

New Setting

VAL

Programming the Mode Registers (Cont’d)

The mode register contents can be changed using the same command and timing requirements during normal operation as

long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed

and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the

functionality and/or modes.

Mode Register MR0

The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include

various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by

asserting low on

, RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

NT5CC64M16GP-DINA Scheda tecnica(PDF) 16 Page - Nanya Technology Corporation.