SC202FEVB datasheet(13/17 Pages) SEMTECH

13 / 17 page

SC202F

output capacitor to ensure the capacitance will be

adequate.

Table 2 lists the manufacturers of recommended output

capacitor options.

Table 2 — Recommended Output Capacitors

Manufacturer

Part Number

Value

(μF)

Type

Rated

Voltage

(VDC)

Dimensions

LxWxH (mm)

Case Size

Murata

GRM188R60J106ME47D

10±20%

X5R

6.3

1.6x0.8x0.8

0603

Murata

GRM21BR60J106K

10±10%

X5R

6.3

2.0x1.25x1.25

0805

Taiyo Yuden

JMK107BJ106MA-T

10±20%

X5R

6.3

1.6x0.8x0.8

0603

TDK

C1608X5R0J106MT

10±20%

X5R

6.3

1.6x0.8x0.8

0603

Selection

The SC202F input source current will appear as a DC

supply current with a triangular ripple imposed on it. To

prevent large input voltage ripple, a low ESR ceramic

capacitor is required. A minimum value of 4.7μF should

be used. It is important to consider the DC voltage coeffi-

cient characteristics when determining the actual required

value. For example, a 10μF, 6.3V, X5R ceramic capacitor

with 5V DC applied may exhibit a capacitance as low as

4.5μF. The value of required input capacitance is estimated

by determining the acceptable input ripple voltage and

calculating the minimum value required for C

using the

equation

ESR

OUT

The input voltage ripple is at maximum level when the

input voltage is twice the output voltage (50% duty cycle

scenario).

The input capacitor provides a low impedance loop for

the edges of pulsed current drawn by the PMOS switch.

Low ESR/ESL X5R ceramic capacitors are recommended

for this function. To minimize stray inductance, the capaci-

Applications Information (continued)

tor should be placed as closely as possible to the IN and

GND pins. Table 3 lists recommended input capacitor

options from different manufacturers.

Table 3 — Recommended Input Capacitors

Manufacturer

Part Number

Value

(μF)

Type

Rated

Voltage

(VDC)

Dimensions

LxWxH (mm)

Case Size

Murata

GRM188R60J475K

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

Murata

GRM188R60J106K

10±10%

X5R

6.3

1.6x0.8x0.8

0603

Taiyo Yuden

JMK107BJ475KA

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

TDK

C1608X5R0J475KT

4.7±10%

X5R

6.3

1.6x0.8x0.8

0603

PCB Layout Considerations

The layout diagram in Figure 3 shows a recommended

PCB top-layer for the SC202F and supporting compo-

nents.

Specified layout rules must be followed since the

layout is critical for achieving the performance specified in

the Electrical Characteristics table. Poor layout can

degrade the performance of the DC-DC converter and can

contribute to EMI problems, ground bounce, and resistive

voltage losses. Poor regulation and instability can also

result.

The following guidelines are recommended for designing

a PCB layout:

should be placed as close to the IN and GND pins

as possible. This capacitor provides a low impedance

loop for the pulsed currents present at the buck

converter’s input. Use short wide traces to minimize

trace impedance. This will also minimize EMI and

input voltage ripple by localizing the high frequency

current pulses.

OUT

should be connected as closely as possible to the

OUT pin.

Use a ground plane referenced to the GND pin. Use

several vias to connect to the component side ground

to further reduce noise and interference on sensitive

circuit nodes.

Route the output voltage feedback/sense trace

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