AW9201

Nov 2017 V1.1

www.awinic.com.cn

8

Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD

0

A2 A1 A0

A6 A5

A3

A4

A4 A3

A1

A2

A7

A5

A6

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

D5 D4

D2

D3

A0

D6

D7

D1 D0

7

8

0

1

2

3

4

5

6

7

8

SCL

SDA

Ack

Ack

Start

R/W

Stop

Device Address

Register Address

Write Data

Read Cycle

In a read cycle, the following steps should be followed:

a)

Master device generates START condition

b)

Master device sends slave address (7-bit) and the data direction bit (r/w = 0).

c)

Slave device sends acknowledge signal if the slave address is correct.

d)

Master sends control register address (8-bit)

e)

Slave sends acknowledge signal

f)

Master generates STOP condition followed with START condition or REPEAT START condition

g)

Master device sends slave address (7-bit) and the data direction bit (r/w = 1).

i)

Slave device sends acknowledge signal if the slave address is correct.

j)

Slave sends data byte from addressed register.

k)

If the master device sends acknowledge signal, the slave device will increase the control register

address by one, then send the next data from the new addressed register.

l)

If the master device generates STOP condition, the read cycle is ended.

0

A2

A1

A0

A6

A5

A3

A4

A4

A3

A1

A2

A7

A5

A6

1

2

3

4

5

6

7

8

0

1

2

3

4

5

6

A4

A3

A1

A2

A0

A5

A6

D6

D0

D1

A0

D7

7

0

1

2

3

4

5

6

7

8

0

1

...

6

SCL

SDA

Ack

Ack

Ack

7

8

Ack

start

R/W

……

stop

Device Address

Register Address

Device Address

Write Data

8

RS

Using

Repeat start

A4

A3

A1

A2

A5

A6

D6

D0

D1

A0

D7

0

1

2

3

4

5

6

7

8

0

1

...

6

Ack

7

8

Ack

……

stop

Write Data

S

Separated

Read/write

transaction

……

……

……

Device Address

P

……

……

R/W

R/W

SDA and SCL

The two interface line SCL and SDA should be connected to a positive supply, via a pull-up resistor and

remain HIGH even when the bus is idle.

The pull-

up resistor can be selected in the range of 1k~10KΩ to make the rising time fit with the requirement

compatible standard. The typical value is 4.7KΩ.

AW9201 can support different high level (1.8V~3.3V) of this two-wire interface. And deglitch circuit is also

implemented inside to filter out the glitch in the SCL, SDA line.