Detailed Description

The MAX16152/MAX16153/MAX16154/MAX16155 are ultra-low-current supervisory circuits that monitor a single system

supply voltage and assert an active-low reset signal when the supply voltage drops below the factory-trimmed reset

threshold. After the supply voltage rises above the threshold voltage, the reset output remains asserted during the

reset timeout period, and finally asserts after the timeout period ends. In addition, a watchdog timer circuit monitors

microprocessor or microcontroller activity. During normal operation, the microprocessor or microcontroller toggles the

WDI input periodically with a valid logic transition (low to high or high to low). If the WDI input is toggled within

input is not strobed before the timeout period expires, the watchdog output is asserted low for a period equal to the

Input Threshold

supply voltage ranges. The input threshold is programmable from 1.5V to 5V in approximately 100mV increments.

Contact Maxim for thresholds not listed in the Ordering Information table.

Watchdog

The MAX16152/MAX16153/MAX16154/MX16155 offer flexible watchdog circuits for monitoring microprocessor or

microcontroller activity. During normal operation, the internal timer is cleared and restarted each time the WDI input

as the WDI input is strobed within the selected timeout period. If the WDI input is not strobed before the timeout period

feature a logic input to enable/disable the watchdog timer during normal operation while the MAX16152 and MAX16153

does not. The watchdog timer for the MAX16152 and MAX16153 can be disabled by leaving the WDI floating.

Watchdog Startup Delay

All devices feature a factory-set startup delay. The startup delay provides an initial delay for the watchdog timer circuit

to power up and initialize before assuming responsibility for normal watchdog input monitoring. For the MAX16152 and

MAX16153, monitoring of the WDI input begins after the start-up time is complete. For the MAX16154 and MAX16155,

monitoring of the WDI input begins after the start-up delay if WD_EN is pulled high. To ensure that the system generates

no undesired watchdog outputs, the routine watchdog input transitions should begin before the minimum startup delay

period has expired. The startup delay is activated after the reset output is de-asserted. See the Selector Guide for

available watchdog startup delay options.

Watchdog Timeout Period

An open-drain, active-low watchdog output (WDO) asserts if a valid watchdog input transition is not received before the

timeout period elapses. See the Selector Guide for available watchdog timeout period options.

Watchdog Enable Input (WD_EN)

The MAX16154 and MAX16155 feature an active-high logic input (WD_EN) to enable or disable the watchdog function.

Applying a logic-low to WD_EN disables the watchdog function, causing the MAX16154 and MAX16155 to ignore any

signals applied to WDI. Applying a logic-high to WD_EN enables the watchdog function after 300μs (max) of set up time

MAX16152/MAX16153/

MAX16154/MAX16155

nanoPower Supervisor and Watchdog Timer

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