GD5F1GQ4REFIS datasheet(9/60 Pages) GIGADEVICE

Il numero della parte	GD5F1GQ4REFIS

Spiegazioni elettronici	SPI(x1/x2/x4) NAND Flash

PDF	60 Pages

Scroll/Zoom	100%

Produttore elettronici	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Homepage	http://www.gigadevice.com/

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9 / 60 page

SPI(x1/x2/x4) NAND Flash

ARRAY ORGANIZATION

Each block has

Each page has

128K+8K

2K+128

bytes

pages

blocks

Figure3-1. Array Organization

2048

128

2048

128

1 block

1 block = (2K + 128 bytes) x 64 pages

= (128K + 8K) bytes

1 page

= (2K + 128 bytes)

Cache Register

Data Register

Per device:

1Gb: 1024blocks

1 device:

For 1Gb = (128K + 8K) bytes x 1024 blocks

= 1Gb

Internal ECC = OFF

2048

1 block

1 block = (2K + 64 bytes) x 64 pages

= (128K + 4K) bytes

1 page

= (2K + 64 bytes)

Cache Register

Data Register

Per device:

1Gb: 1024blocks

1 device:

For 1Gb = (128K + 4K) bytes x 1024 blocks

= 1Gb

Internal ECC= ON

Note:

1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the

last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area.

2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area.

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