GD5F1GQ4REFJS datasheet(38/60 Pages) GIGADEVICE

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SPI(x1/x2/x4) NAND Flash

12 RESET OPERATIONS

12.1 Soft Reset (FFH)

Figure12-1. Reset Sequence Diagram

Command

FFH

CS#

SCLK

High-Z

The RESET (FFH) command stops all operations. For example, in case of a program or erase or read operation, the reset

command can make the device enter the wait state. The device will automatically read first page of fist block to cache after

RESET (FFH)

During a cache program or cache read, a reset can also stops the previous operation and the pending operation. The OIP

status can be read from 300ns after the reset command is sent.

12.2 Hardware RESET

12.2.1 Hardware RESET Function

The RESET# pin allows the device to be reset by the host controller or system reset timer like watchdog for re-boot

without a power off and on sequence.

For the 8-pin package, pin7 can be configured as a RESET# pin depending on the status register setting, QE=0 and

HOLD/RST=1(see Section Hardware RESET Setting). On the 16-pin/24-pin package, a dedicated RESET# pin is provided

and it is independent of QE bit setting (see Section Hardware RESET Setting).

The RESET# pin goes low for a period of tRLRH or longer will reset the flash memory. After a reset cycle, the flash is

at the following states:

-In standby mode

-All the volatile bits return to the default value as after power-on-reset.

-Data of page0/block0 is read out to the cache, user can issue read from cache command (03/0B/3B/6B/BB/EB) for

data.

Please note that No command is accepted during the reset cycle (tRB1 or tRB2).

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