GD25B256DFIS datasheet(60/82 Pages) GIGADEVICE

60 / 82 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B256D

Figure 70 Read Security Registers command Sequence Diagram (ADS=1)

7.36.

Enable Reset (66H) and Reset (99H)

If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its

default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch

status (WEL), Program/Erase Suspend status, Continuous Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4).

The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command

sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending

Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately

tRST / tRST_E to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going

or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is

recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.

Figure 71 Enable Reset and Reset command Sequence Diagram

Command

66H

CS#

SCLK

High-Z

Command

99H

Command

48H

CS#

SCLK

High-Z

9 10

36 37 38 39

31 30 29

32-bit address

MSB

Data Out1

50 51 52 53

54 55

Data Out2

CS#

SCLK

MSB

Dummy Byte

42 43 44 45

46 47

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