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GD25B257D Scheda tecnica(PDF) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B257D Scheda tecnica(HTML) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
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16 / 92 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25B257D 16 7.2. Extended Address Register Table 11. Extended Address Register No. Name Description Note EA0 A24 Address bit Volatile writable EA1 Reserved Reserved Reserved EA2 ECS ECC Correction Signal bit Volatile writable EA3 DLP Data Learning Pattern Enable bit Volatile writable EA4 Reserved Reserved Reserved EA5 Reserved Reserved Reserved EA6 DED Double Error Detection bit Volatile, read only EA7 SEC Single Error Correction bit Volatile, read only In addition to the Status Registers, GD25B257D provides a volatile Extended Register which consists of the configuration bits for advanced features and the MSB address bit A24. Upon power up or after the execution of a Software/Hardware Reset, the Extended Register values will be cleared to 0. There are two different commands to write the Extended Register. 56H is used to write EA5-EA2 bits, A24 value will not be changed. To change A24 bit setting, C5H should be used, and EA5-EA2 bit values will not be affected. A24 bit The Extended Address Bit A24 is used only when the device is operating in the 3-Byte Address Mode (ADS=0), which is volatile writable by C5H command. The lower 128Mb memory array (00000000H – 00FFFFFFH) is selected when A24=0, and all instructions with 3-Byte addresses will be executed within that region. When A24=1, the upper 128Mb memory array (01000000H – 01FFFFFFH) will be selected. If the device powers up with ADP bit set to 1, or an “Enter 4-Byte Address Mode (B7H)” instruction is issued, the device will require 4-Byte address input for all address related instructions, and the Extended Address Bit A24 setting will be ignored. However, any instruction with 4-Byte address input will replace the Extended Address Bit A24 with new settings. SEC, DED bits SEC (Single Error Correction) and DED (Double Error Detection) Status Bits are used to show the ECC results for the last Read operation. SEC and DED bits will be cleared to 0 once the device accepts a new Read command. SEC, DED Definitions 00 No ECC events in all aligned 8-Byte granularities 10 SEC events in single or multiple 8-Byte granularities, and the data is OK to use. (Unless it contains more than one odd bit errors in 8-Byte granularity) 01 DED events in single or multiple 8-Byte granularities, and the data contains 2 or more even bit errors. 11 Both SEC & DED occurred in multiple 8-Byte granularities, and the data contains 2 or more bit errors. |
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