GD25B127DPJS datasheet(37/65 Pages) GIGADEVICE

37 / 65 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

7.28.

Read Unique ID (4BH)

The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The

Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system.

The Read Unique ID command sequence: CS# goes low  sending Read Unique ID command  3-Byte Address

(000000H) Dummy Byte128bit Unique ID Out CS# goes high.

Figure31. Read Unique ID Sequence Diagram (ADS=0)

Command

4BH

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

(000000H)

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

7.29.

Erase Security Registers (44H)

The GD25B127D provides three 1024-byte Security Registers which can be erased and programmed individually.

These registers may be used by the system manufacturers to store security and other important information separately from

the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command

must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low  sending Erase Security Registers command 

3-byte address on SI CS# goes high. The command sequence is shown in Figure32. CS# must be driven high after the

eighth bit of the last address byte has been latched in; otherwise the Erase Security Registers command is not executed.

As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the

Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress

(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is

completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security

Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set

to 1, the Security Registers will be permanently locked; the Erase Security Register command will be ignored.

Address

A23-16

A15-12

A11-10

A9-0

Security Register #1

00H

0 0 0 1

0 0

Don

’t care

Security Register #2

00H

0 0 1 0

0 0

Don

’t care

Security Register #3

00H

0 0 1 1

0 0

Don

’t care

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