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GD25D40CSFG Scheda tecnica(PDF) 24 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25D40CSFG Scheda tecnica(HTML) 24 Page - GigaDevice Semiconductor (Beijing) Inc. |
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24 / 43 page ![]() 3.3V Uniform Sector Standard and Dual Serial Flash GD25D40C/20C 24 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Figure19. Power-On Timing Sequence Diagram Table 3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min. Max. Unit tVSL VCC(min.)to device operation 0.3 ms VWI Write Inhibit Voltage 1.5 2.5 V VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 0.5 V tPWD The minimum duration for ensuring initialization will occur 300 us 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3. ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 -40 to 105 -40 to 125 ℃ Storage Temperature -65 to 150 ℃ Transient Input / Output Voltage (note: overshoot) -2.0 to VCC+2.0 V Applied Input/Output Voltage -0.6 to VCC+0.4 V VCC -0.6 to 4.2 V VCC(max.) VCC(min.) tVSL Chip Selection is not allowed Full Device Access Allowed Time VPWD(max.) tPWD VCC |
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