GD25B127DPFS datasheet(27/65 Pages) GIGADEVICE

27 / 65 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25B127D

7.15.

Quad Page Program (32H)

The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. A Write

Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the

Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the command

code (32H), three address bytes and at least one data byte on IO pins.

The command sequence is shown in Figure17. If more than 256 bytes are sent to the device, previously latched data

are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than

256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on

the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in;

otherwise the Quad Page Program (PP) command is not executed.

As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the

Quad Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP)

bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1,

and BP0) is not executed.

Figure17.Quad Page Program Sequence Diagram

Command

32H

CS#

SCLK

9 10

28 29 30 31

23 22 21

24-bit address

32 33 34 35

MSB

36 37 38 39

SI(IO0)

SO(IO1)

IO2

IO3

Byte1 Byte2

CS#

SCLK

SI(IO0)

SO(IO1)

IO2

IO3

42 43 44 45

46 47

50 51 52 53

54 55

Byte11

Byte12

Byte253

Byte256

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