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GD25LE40CEIG Scheda tecnica(PDF) 60 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LE40CEIG Scheda tecnica(HTML) 60 Page - GigaDevice Semiconductor (Beijing) Inc. |
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60 / 75 page ![]() 1.8V Uniform Sector Dual and Quad Serial Flash GD25LE40C/20C/10C/05C 60 Figure39. Serial Input Timing SCLK CS# SI MSB SO High-Z LSB tCHSL tSLCH tDVCH tCHDX tSHCH tCHSH tCHCL tCLCH tSHSL Figure40. Output Timing Figure41. Resume to Suspend Timing Diagram CS# Resume Command tRS Suspend Command Figure42. Hold Timing CS# SCLK SO SI Least significant address bit (LIB) in tCLQV tCLQX tCLQX tCLQV tCLH tCLL tSHQZ LSB CS# SCLK SO HOLD# tCHHL tHLQZ tHLCH tCHHH tHHCH tHHQX SI do not care during HOLD operation. |
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