GD25LE40CEEG datasheet(10/75 Pages) GIGADEVICE

10 / 75 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LE40C/20C/10C/05C

DEVICE OPERATION

SPI Mode

Standard SPI

The GD25LE40C/20C/10C/05C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select

(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched

on the rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI

The GD25LE40C/20C/10C/05C supports Dual SPI operation when using the

“Dual Output Fast Read” and “Dual I/O Fast

Read

” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at twice the rate of

the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

Quad SPI

The GD25LE40C/20C/10C/05C supports Quad SPI operation when using the

“Quad Output Fast Read” (6BH),” Quad I/O

Fast Read” (EBH) commands. These commands allow data to be transferred to or from the device at four times the rate of

the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and

WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status

Hold

The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if

SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of

HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).

The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD

operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and

then CS# must be at low.

Figure1. Hold Condition

HOLD

CS#

SCLK

HOLD#

GD25LE40CEEG Scheda tecnica(PDF) 10 Page - GigaDevice Semiconductor (Beijing) Inc.