U74HC4046AL-P16-R datasheet(12/19 Pages) UTC

12 / 19 page

U74HC4046A

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

12 of 19

www.unisonic.com.tw

QW-R502-461.D



PHASE COMPARATORS (Cont.)

Phase comparator 3 (PC3)

This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. If this comparator is used,

the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. The

transfer characteristic of PC3, assuming ripple (fr = fj) is suppressed, is:

)

(

COMPIN

SIGIN

DEMOUT









where VDEMOUT = VPC3OUT (via low-pass filter).

The phase comparator gain is:

)

V /

(





As shown in Fig.5, the average output voltage from PC3, fed to the low-pass filter and seen at the demodulator

output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN. As shown in Fig.6, it is the

typical waveforms for the PC3 loop locked at fo.

VCC

VDEMOUT(AV)

1/2VCC

DEMOUT

360

180

VDEMOUT =VPC3OUT =

VCC

( SIGIN -

COMPIN)

DEMOUT = ( SIGIN -

COMPIN)



Fig.5 Phase comparator 3: average output voltage versus input phase difference.

Fig.6 Typical waveforms for PLL using phase comparator 3, loop locked at fo.

The phase-to-output response characteristic of PC3 (Fig.5) differs from that of PC2, as the phase angle

between SIGIN and COMPIN varies between 0

o and 360o and 180o is the centre frequency. And the voltage swing of

PC3 is greater than that of PC2 for input phase differences, but as a consequence the ripple content of VCO input

signal is higher. Both of the PLL lock range and capture range of this type of phase comparator are dependent on

the low-pass filter. The VCO adjusts to its lowest frequency via PC3, when no signal present at SIGIN.

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