GD25Q64CPJS datasheet(21/74 Pages) GIGADEVICE

Il numero della parte	GD25Q64CPJS

Spiegazioni elettronici	3.3V Uniform Sector Dual and Quad Serial Flash

PDF	74 Pages

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Produttore elettronici	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Homepage	http://www.gigadevice.com/

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21 / 74 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q64C

7.9.

Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is latched

in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0.

The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of

Status Register (S9) must be set to enable for the Quad Output Fast Read command.

Figure 10. Quad Output Fast Read Sequence Diagram

Command

6BH

CS#

SCLK

SI(IO0)

SO(IO1)

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

34 35 36 37

38 39

Byte1

42 43 44 45

46 47

Dummy Clocks

WP#(IO2)

High-Z

HOLD#(IO3)

High-Z

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

Byte2 Byte3 Byte4

GD25Q64CPJS Scheda tecnica(PDF) 21 Page - GigaDevice Semiconductor (Beijing) Inc.