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GD25Q40CSFG Scheda tecnica(PDF) 52 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q40CSFG Scheda tecnica(HTML) 52 Page - GigaDevice Semiconductor (Beijing) Inc. |
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52 / 64 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q40C 52 Read tSUS CS# High To Next Command After Suspend 20 μs tRS Latency Between Resume And Next Suspend 100 μs tRST CS# High To Next Command After Reset (Except From Erase) 30 μs tRST_E CS# High To Next Command After Reset (From Erase) 12 ms tW Write Status Register Cycle Time 5 30 ms tBP1 Byte Program Time (First Byte) 30 60 μs tBP2 Additional Byte Program Time (After First Byte) 2.5 15 μs tPP Page Programming Time 0.6 4 ms tSE Sector Erase Time (4K Bytes) 45 400 ms tBE1 Block Erase Time (32K Bytes) 0.15 1.6 s tBE2 Block Erase Time (64K Bytes) 0.25 3.0 s tCE Chip Erase Time (GD25Q40C) 2.5 10 s Note: 1. Typical values given for TA=25°C. 2. Value guaranteed by design and/or characterization, not 100% tested in production. |
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