GD25WD40CSIG datasheet(17/49 Pages) GIGADEVICE

17 / 49 page

Uniform Sector

Standard and Dual Serial Flash

GD25WD40C/20C

Figure4. Write Status Register Sequence Diagram

7.5. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit being latched-in on

the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at

a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore,

be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase,

Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure5. Read Data Bytes Sequence Diagram

7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte

address (A23-A0) and a dummy byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content,

at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fC, on the falling edge of SCLK. The

first byte addressed can be at any location. The address is automatically incremented to the next higher address after each

byte of data is shifted out.

Command

03H

CS#

SCLK

High-Z

9 10

28 29 30 31 32

MSB

34 35 36 37

23 22 21

38 39

24-bit address

MSB

Data Out1

Data Out2

Command

01H

CS#

SCLK

High-Z

9 10 11 12 13 14 15

MSB

Status Register in

GD25WD40CSIG Scheda tecnica(PDF) 17 Page - GigaDevice Semiconductor (Beijing) Inc.