T25D32ASEPR datasheet(58/74 Pages) HMSEMI

58 / 74 page

Note: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-byte SFDP Register.

Figure 7.32 Read SFDP Register Instruction

7.5.6 Erase Security Registers (44h)

The

HM25Q128A offers three 256-byte Security Registers which can be erased and programmed

individually. These registers may be used by system manufacturers to store security and other important

information separately from the main memory array.

The Erase Security Register command is similar to the Sector Erase command. A Write Enable

command must be executed before the device will accept the Erase Security Register Command (Status

instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the security registers.

Address

A23-16

A15-8

A7-0

Security Register-1

00h

10h

xxh

Security Register-2

00h

20h

xxh

Security Register-3

00h

30h

xxh

Note:

1. Addresses outside the ranges in the table have undefined results.

The Erase Security Register command sequence is shown in Figure 7.33. The CS# pin must be driven

high after the eighth bit of the last byte has been latched. If this is not done the command will not be executed.

After CS# is driven high, the self-timed Erase Security Register operation will commence for a time duration of

tSE (see Section 8.5, AC Electrical Characteristics). While the Erase Security Register cycle is in progress, the

Read Status Register command may still be accessed for checking the status of the BUSY bit. The BUSY bit

is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept

other commands again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit

in the Status Register is cleared to 0. The Security Register Lock Bits (LB[3:1]) in the Status Register-2 can be

used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will

be permanently locked, and an Erase Security Register command to that register will be ignored.

Figure 7.33 Erase Security Registers Instruction

7.5.7 Program Security Registers (42h)

The Program Security Register command is similar to the Page Program command. It allows from one

byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A

Write Enable command must be executed before the device will accept the Program Security Register

Command (Status Register bit WEL= 1). The command is initiated by driving the CS# pin low then shifting the

instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The

CS# pin must be held low for the entire length of the command while data is being sent to the device.

HM25Q128A

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