AD9175 datasheet(29/150 Pages) AD

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Data Sheet

AD9175

Rev. A | Page 29 of 150

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing with many industry-standard

microcontrollers and microprocessors. The serial input/output

is compatible with most synchronous transfer formats, including

both the Motorola, Inc., SPI and Intel® SSR protocols. The interface

allows read and write access to all registers that configure the

AD9175. MSB first or LSB first transfer formats are supported.

The serial port interface can be configured as a 4-wire interface

or a 3-wire interface in which the input and output share a

single pin input/output (SDIO). Data can be transferred either

one byte at a time, with the address specified for each read/write

operation, or can be transferred in multibyte mode, with the

address incremented automatically at the end of each transfer

cycle, thus increasing link throughput when multiple read/write

operations to register addresses are sequential.

SCLK

SDIO

SDO

SPI

PORT

Figure 49. Serial Port Interface Pins (144-Ball BGA_ED)

There are two phases to a communication cycle with the

AD9175. Phase 1 is the instruction cycle (the writing of an

instruction byte into the device), coincident with the first

16 SCLK rising edges. The instruction word provides the serial

port controller with information needed for Phase 2 of the

communication cycle, namely the data transfer cycle. The

instruction word defines the starting register address for the

following data transfer and flags, whether the upcoming data

transfer is a read operation or a write operation.

A logic high on the CS pin followed by a logic low resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next 16 rising SCLK edges represent the

instruction bits of the current input/output operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one or more data bytes. Eight × N SCLK cycles are

required to transfer N bytes during the transfer cycle. The registers

update (latch) their data immediately upon writing to the last

bit of each transfer byte.

The FTW and NCO phase offsets change only when the

frequency tuning word load request bit (DDSM_FTW_

LOAD_REQ or DDSC_FTW_LOAD_REQ) is set.

DATA FORMAT

The instruction byte contains the information shown in Table 14.

Table 14. Serial Port Instruction Word

I15 (MSB)

I[14:0]

R/W

A[14:0]

R/W, Bit 15 of the instruction word, determines whether a read

or a write data transfer occurs after the instruction word write.

Logic 1 indicates a read operation, and Logic 0 indicates a write

operation.

A14 to A0, Bit I14 to Bit I0 of the instruction word, determine

the register that is accessed during the data transfer portion of

the communication cycle.

For multibyte transfers, A[14:0] is the starting address. The

remaining register addresses are generated by the device based

on the address increment bit. If the address increment bits are set

high (Register 0x000, Bit 5 and Bit 2), multibyte SPI writes start on

A[14:0] and increment by 1 every eight bits sent/received. If the

address increment bits are set to 0, the address decrements by 1

every eight bits.

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 80 MHz. All data input is registered on the rising edge

of SCLK. All data is driven out on the falling edge of SCLK.

Chip Select (CS)

An active low input starts and gates a communication cycle.

CS allows more than one device to be used on the same serial

communications lines. The SDIO pin goes to a high impedance

state when this input is high. During the communication cycle,

the chip select must stay low.

Serial Data Input/Output (SDIO)

This pin is a bidirectional data line. In 4-wire mode, this pin

acts as the data input and SDO acts as the data output.

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