LT4293IMSPBF datasheet(13/16 Pages) AD

13 / 16 page

LT4293

Rev. 0

For more information www.analog.com

an auxiliary power input, install a TVS between VIN and

GND. See Layout Considerations for TVS placement.

For extremely high cable discharge and surge protection,

contact Analog Devices Applications.

Exposed Pad

The LT4293 DFN package has an exposed pad that is

internally connected to GND. The exposed pad may only

be connected to GND on the printed circuit board.

TYPICAL APPLICATIONS

4293 TA03

LT4321

TG36

BG12

PSMN075-100MSE ×4

WURTH 749022016

BG36

IN36

IN45

IN78

IN12

DATA

PAIRS

SPARE

PAIRS

OUTN

OUTP

SMAJ58A

VPORT

PWRGD

AUX

RCLASS

T2P

RCLASS++

HSGATE

PSMN040-100MSE

LT4293

GND

TG12

BG45

TG78

TG45

BG78

HSSRC

ISOLATED

POWER

SUPPLY

GND

RUN

VOUT

VIN

22µF

–

RCLS

140

RCLS++

46.4

47nF

3.3k

100k

CPD2

0.047µF

CPD1

0.047µF

OPTO

PSE TYPE

(TO µP)

PSE TYPE

T2P RESPONSE ALLOCATED POWER

IEEE 802.3at 25.5W

LOW-Z TO GND

25.5W

IEEE 802.3bt 51W

50% LOW-Z

51W

OR HIGHER POWER

LTPoE++ 52.7W

75% LOW-Z

52.7W

OR HIGHER POWER

LTPoE++/IEEE 802.3bt-Compliant > 99% Efficient 51W Powered Device

LAYOUT CONSIDERATIONS

Avoid excessive parasitic capacitance on the RCLASS

and RCLASS++ pins and place resistors RCLS and RCLS++

close to the LT4293.

It is strictly required for maximum protection to place the

0.1μF input capacitor, CPD, and transient voltage suppres-

sor as close to the LT4293 as possible. When operating

the LT4293 with the LT4321, place a 0.047μF capacitor,

CPD1, as close as possible to the LT4293 VPORT and

GND pins (pin 10 and pin 5, respectively), and a 0.047μF

capacitor, CPD2, as close as possible to the LT4321 OUTP

and OUTN pins.

APPLICATIONS INFORMATION

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