COPCH940C datasheet(12/26 Pages) NSC

12 / 26 page

Connection Diagrams (Continued)

Pin Descriptions

CC and GND are the power supply pins.

CKI is the clock input. This can come from an external

source, a R/C generated oscillator or a crystal (in conjunc-

tion with CKO). See Oscillator description.

RESET is the master reset input. See Reset description.

PORT I is a four bit Hi-Z input port.

PORT L is an 8-bit I/O port.

There are two registers associated with each L I/O port: a

data register and a configuration register. Therefore, each L

I/O bit can be individually configured under software control

as shown below:

Port L

Config.

Port L

Data

Port L

Setup

Hi-Z Input (TRI-STATE)

Input With Weak Pull-Up

Push-Pull “0” Output

Push-Pull “1” Output

Three data memory address locations are allocated for

these ports, one for data register, one for configuration reg-

ister and one for the input pins.

PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input

pins (G6, G7). All eight G-pins have Schmitt Triggers on the

inputs. The G7 pin functions as an input pin under normal

operation and as the continue pin to exit the HALT mode.

There are two registers with each I/O port: a data register

and a configuration register. Therefore, each I/O bit can be

individually configured under software control as shown be-

low.

Port G

Config.

Port G

Data

Port G

Setup

Hi-Z Input (TRI-STATE)

Input With Weak Pull-Up

Push-Pull “0” Output

Push-Pull “1” Output

Three data memory address locations are allocated for

these ports, one for data register, one for configuration reg-

ister and one for the input pins. Since G6 and G7 are input

only pins, any attempt by the user to set them up as outputs

by writing a one to the configuration register will be disre-

garded. Reading the G6 and G7 configuration bits will return

zeros. Note that the chip will be placed in the HALT mode by

setting the G7 data bit.

Six bits of Port G have alternate features:

INTR (an external interrupt)

TIO (timer/counter input/output)

SO (MICROWIRE serial data output)

SK (MICROWIRE clock I/O)

SI (MICROWIRE serial data input)

CKO crystal oscillator output (selected by mask option)

or HALT restart input (general purpose input)

Pins G1 and G2 currently do not have any alternate func-

tions.

PORT D is a four bit output port that is set high when RESET

goes low. Care must be exercised with the D2 pin operation.

At RESET, the external load on this pin must ensure that the

output voltage stays above 0.9 V

CC to prevent the device

from entering special modes. Also, keep the external loading

on the D2 pin to less than 1000 pf.

Functional Description

Figure 1 shows the block diagram of the internal architec-

ture. Data paths are illustrated in simplified form to depict

how the various logic elements communicate with each

other in implementing the instruction set of the device.

ALU AND CPU REGISTERS

The ALU can do an 8-bit addition, subtraction, logical or shift

operation in one cycle time.

There are five CPU registers:

A is the 8-bit Accumulator register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is the 8-bit address register, can be auto incremented or

decremented.

X is the 8-bit alternate address register, can be incremented

or decremented.

SP is the 8-bit stack pointer, points to subroutine stack (in

RAM).

B, X and SP registers are mapped into the on chip RAM. The

B and X registers are used to address the on chip RAM. The

SP register is used to address the stack in RAM during sub-

routine calls and returns.

PROGRAM MEMORY

Program memory for the COP820C family consists of 1024

bytes of ROM (2048 bytes of ROM for the COP840C family).

These bytes may hold program instructions or constant data.

20 DIP/SO

DS009103-6

28 DIP/SO

DS009103-8

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