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ADV7330 Scheda tecnica(PDF) 30 Page - Analog Devices

Il numero della parte ADV7330
Spiegazioni elettronici  Multiformat 11-Bit Triple DAC Video Encoder
PDF  76 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADV7330 Scheda tecnica(HTML) 30 Page - Analog Devices

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REV. B
–30–
ADV7330
Table IV. Async Timing Mode Truth Table
Reference in
HSYNC_I/P
VSYNC_I/P
BLANK_I/P*
Figures 20a and 20b
1
→ 0
0
0 or 1
50% point of falling edge of tri-level horizontal sync signal
a
00
→ 1
0 or 1
25% point of rising edge of tri-level horizontal sync signal
b
0
→ 1
0 or 1
0
50% point of falling edge of tri-level horizontal sync signal
c
10 or 1
0
→ 1
50% start of active video
d
10 or 1
1
→ 0
50% end of active video
e
*When async timing mode is enabled, BLANK_I/P (Pin 25) becomes an active high input.
BLANK_I/P is set to active low at Address 10h, Bit 6.
HD Timing Reset
[Address 14h, Bit 0]
A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. When this bit is set back to
0, the internal counters will commence counting again. PLL must
be powered off by this mode.
The minimum time the pin has to be held high is one clock cycle,
otherwise this reset signal might not be recognized. This timing
reset applies to the HD timing counters only.



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