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CS61318 Scheda tecnica(PDF) 27 Page - Cirrus Logic |
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CS61318 Scheda tecnica(HTML) 27 Page - Cirrus Logic |
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27 / 28 page ![]() CS61318 DS441PP2 27 Control & Monitor Frame Format Encoder/ Decoder CS61318 IN HARDWARE MODE 28 1 26 27 5 7 6 8 3 4 2 9 10 + 33 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+ TAOS MCLK RLOOP LLOOP MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 RTIP RRING TRING TTIP 24 25 12 23 LOS NLOOP 11 JASEL RECEIVE LINE 19 20 R1 R2 1 5 2 6 T1 1:1 0.47 µF TRANSMIT LINE 16 13 0.47 µF 2 6 1 5 R3 R4 SD I SDO T2 1:N Figure 13. Hardware Mode Configuration NOTE: The 0.47 µF capacitor between R1 & R2 may be omitted if common mode noise is not an issue. NOTE: The optional 0.47 µF DC blocking cap eliminates DC saturation current through T2 E1 75 Ω Coaxial Cable E1 120 Ω Twisted Pair R1 ( Ω) 37.5 60 R2 ( Ω) 37.5 60 R3 ( Ω) 15 15 R4 ( Ω) 15 15 T2 1:1.58 1:2 |
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