TABLE 6. READ — 6800 µP Interface Parameters (Continued)

No.

Parameter

Min

Typ

Max

Units

T15

MasterOUT

Recovery Time

5

ns

T16

MasterOUT

INTR Response, (Note 5)

0

MC Cycles

For the MOT CPU 68xx mode, the Master accepts data on the CS* Low-to-High transition or the E High-to-Low transition, which

ever come first. The Slave output only uses the CS* pin for data strobe/latch, as the E signal is held constantly High.

CPU MODE — WRITE — i80

TABLE 7. WRITE — 80xx µP Interface Parameters

No.

Parameter

Min

Typ

Max

Units

T1

MasterIN

Data Setup before Write* High

5

ns

T2

MasterIN

Data Hold after Write* High

5

ns

T3

MasterIN

Write* Recovery Time, (Note 5)

6

MC Cycles

T4

Master

Master Latency

5

MC Cycles

T5

Slave

Slave Latency

9

MC Cycles

T6

SlaveOUT

Data Valid before Write* High-to-Low

1

MC Cycles

T7

SlaveOUT

WR* Pulse Width Low

3

MC Cycles

T8

SlaveOUT

Data Valid before Write* Low-to-High

4

MC Cycles

T9

SlaveOUT

Data Valid after Write* Low-to-High

1

MC Cycles

20093312

FIGURE 15. WRITE — 80xx µP Interface

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