56F802 datasheet(5/40 Pages) FREESCALE

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56F802 Description

56F802 Technical Data, Rev. 7

Freescale Semiconductor

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Computer-Operating Properly (COP) watchdog timer

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External interrupts via GPIO

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Trimmable on-chip relaxation oscillator

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External reset pin for hardware reset

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JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

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Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock

1.1.4

Energy Information

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Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

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Uses a single 3.3V power supply

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On-chip regulators for digital and analog circuitry to lower cost and reduce noise

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Wait and Stop modes available

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Integrated power supervisor

1.2 56F802 Description

The 56F802 is a member of the 56800 core-based family of processors. It combines, on a single chip, the

processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to

create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and

compact program code, the 56F802 is well-suited for many applications. The 56F802 includes many

peripherals that are especially useful for applications such as motion control, home appliances, encoders,

tachometers, limit switches, power supply and control, engine management, and industrial control for

power, lighting, automation and HVAC.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in

parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming

model and optimized instruction set allow straightforward generation of efficient, compact code for both

DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid

development of optimized control applications.

The 56F802 supports program execution from either internal or external memories. Two data operands can

be accessed from the on-chip Data RAM per instruction cycle. The 56F802 also provides and up to 4

General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56F802 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each

programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K

words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines

that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash

memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory

can also be either bulk or page erased.

A key application-specific feature of the 56F802 is the inclusion of a Pulse Width Modulator (PWM)

module. This modules incorporates six complementary, individually programmable PWM signal outputs

to enhance motor control functionality. Complementary operation permits programmable dead-time

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