PC133 Clock Generator for SiS630/Pentium
®III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07035 Rev. **
05/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
Page 13 of 18
http://www.cypress.com
APPROVED PRODUCT
C9630
AC Parameters
133 MHz Host
100 MHz Host
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
TPeriod
CPU(0:2) period
7.45
8.0
9.98
10.5
nS
5, 6, 8
THIGH
CPU(0:2) high time
1.87
-
3.0
-
nS
6,10
TLOW
CPU(0:2) low time
1.67
-
2.8
-
nS
6, 11
Tr / Tf
CPU(0:2) rise and fall times
0.4
1.9
0.4
2.1
nS
6, 7
TSKEW0
Any CPU to Any CPU Skew time
-
175
-
175
pS
6, 8, 9
TCCJ
CPU(0:2) Cycle to Cycle Jitter
-
250
-
250
pS
6,8,9,14
TPeriod
SDRAM[0:13] period
7.46
8.0
9.89
10.5
nS
5, 6, 8
THIGH
SDRAM[0:13] high time
1.87
-
3.0
-
nS
6,10
TLOW
SDRAM[0:13] low time
1.67
-
2.63
-
nS
6, 11
Tr / Tf
SDRAM[0:13] rise and fall times
0.4
1.69
0.4
1.88
nS
6, 7
TSKEW1
Any SDRAM to Any SDRAM
-
500
-
500
pS
6, 8, 9
TCCJ
SDRAM[0:13] Cycle to Cycle Jitter
-
250
-
250
pS
6,8,9,14
TPeriod
PCI(0:6) period
29.93
-
29.94
-
nS
5, 6, 8
THIGH
PCI(0:6) period
12.0
-
12.0
-
nS
6,10
TLOW
PCI(0:6) low time
12.0
-
12.0
-
nS
6, 11
Tr / Tf
PCI(0:6) rise and fall times
0.5
2.9
0.5
2.9
nS
6, 7
TSKEW2
(Any PCI clock) to (Any PCI clock)
-
500
-
500
pS
6, 8, 9
TCCJ
PCI(0:6) Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
48MHz period ( conforms to
+167ppm max)
20.8212
20.8333
20.8299
20.8442
nS
5, 6, 8
Tr / Tf
48MHz rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
48MHz Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
24MHz period
41.6087
41.6666
41.6026
41.6666
nS
5, 6, 8
Tr / Tf
24MHz rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
24 MHz Cycle to Cycle Jitter
-
500
-
500
pS
6, 8, 9
TPeriod
REF(0:1) period
69.8167
71.0
69.8017
71.0
nS
5, 6, 8
Tr / Tf
REF0 rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
Tr / Tf
REF1 rise and fall times
1.0
4.0
1.0
4.0
nS
6, 7
TCCJ
REF(0:1) Cycle to Cycle Jitter
-
1000
-
1000
pS
6, 8
tpZL, tpZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
nS
13
tpLZ, tpHZ
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
nS
13
tstable
All clock Stabilization from power-up
3
3
mS
12
TSKEW3
CPU to SDRAM (see fig.3, p.3)
0
340
0
354
pS
5, 6, 8
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