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LM3311 Scheda tecnica(PDF) 2 Page - National Semiconductor (TI) |
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LM3311 Scheda tecnica(HTML) 2 Page - National Semiconductor (TI) |
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2 / 29 page ![]() Connection Diagram 20126304 LLP-24 (Top View) θ JA=37˚C/W Ordering Information Order Number Spec. Package Type NSC Package Drawing Supplied As LM3311SQ LLP-24 SQA24A 1000 units/reel tape and reel LM3311SQX LLP-24 SQA24A 4500 units/reel tape and reel LM3311SQ NOPB LLP-24 SQA24A 1000 units/reel tape and reel LM3311SQX NOPB LLP-24 SQA24A 4500 units/reel tape and reel Pin Descriptions Pin Name Function 1 NC Not internally connected. 2 VGHM Output of GPM circuit. This output directly drives the supply for the gate driver circuits. 3 VFLK Determines when the TFT LCD is on or off. This is controlled by the timing controller in the LCD module. 4 VDPM VDPM pin is the enable signal for the GPM block. Pulling this pin high enables the GPM while pulling this pin low disables it. VDPM is used for timing sequence control. 5V DD Reference input for gate pulse modulation (GPM) circuit. The voltage at V DD is used to set the lower VGHM voltage. 6AV IN Op-Amp analog power input. 7 OUT Output of the Op-Amp. 8 NEG Negative input terminal of the Op-Amp. 9 POS Positive input terminal of the Op-Amp. 10 AGND Analog ground for the step-up regulator, LDO, and Op-Amp. Connect directly to DAP and PGND beneath the device. 11 ADJ LDO output voltage feedback input. 12 V OUT LDO regulator output. www.national.com 2 |
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