STR720 datasheet(160/401 Pages) STMICROELECTRONICS

Il numero della parte	STR720

Spiegazioni elettronici	ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES

PDF	401 Pages

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

Homepage	http://www.st.com

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STR720 - ASYNCHRONOUS AHB-APB BRIDGE (A3BRG)

160/401

15 ASYNCHRONOUS AHB-APB BRIDGE (A3BRG)

15.1 Introduction

In order to reduce power consumption, it is possible to use different clock domains depending

on the performances of each block. Typically, the core will run with a fast clock, whereas a

slower clock can be sufficient for most peripherals. Nevertheless, in low power mode, the core

can also be clocked by a slower clock in order just to manage with peripherals requests. The

asynchronous AHB/APB bridge enables to connect completely asynchronous AHB with APB

buses. It implements a synchronization stage that enables to re-synchronize the AHB with the

APB.

The AHB/APB clocks ratio could be typically around 1/10. As a consequence, an APB read

access will need more than 20 AHB cycle to be done.

15.2 Main Features

■

asynchronous AHB/APB clock domains

■

access to up to 13 peripherals with 4 kBytes memory space each.

■

Programmable registers for:

– AHB/APB bridge status

– transaction configuration

– peripherals clock gating

15.3 Functional Description

The asynchronous AHB/APB bridge functionality can be illustrated by Figure 19 on page 161}

STR720 Scheda tecnica(PDF) 160 Page - STMicroelectronics