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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STR720 Scheda tecnica(PDF) 327 Page - STMicroelectronics |
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STR720 Scheda tecnica(HTML) 327 Page - STMicroelectronics |
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327 / 401 page  STR720 - EXTENDED FUNCTION TIMER (EFT) 327/401 Counter Register (CNTR) Address Offset: 10h Reset value: FFFCh This is a 16-bit register that contains the counter value. Control Register 1 (CR1) Address Offset: 14h Reset value: 0000h Bit 15 = EN: Timer Count Enable 0: Timer counter is stopped. 1: Timer counter is enabled. Bit 14 = PWMI: Pulse Width Modulation Input 0: PWM Input is not active. 1: PWM Input is active. Bit 13:12 = Reserved. These bits must be always written to 0. Bit 11 = FOLVB: Forced Output Compare B 0: No effect. 1: Forces OLVLB to be copied to the OCMPB pin. Bit 10 = FOLVA: Forced Output Compare A 0: No effect. 1: Forces OLVLA to be copied to the OCMPA pin. Bit 9 = OLVLB: Output Level B This bit is copied to the OCMPB pin whenever a successful comparison occurs with the OCBR register and OCBE is set in the CR2 register. This value is copied to the OCMPA pin in One Pulse Mode and Pulse Width Modulation mode. Bit 8= OLVLA: Output Level A The OLVLA bit is copied to the OCMPA pin whenever a successful comparison occurs with the OCAR register and the OCAE bit is set in the CR2 register. 15 14 13 12 11 10 9 8 765432 1 0 MSB LSB rrrrrr r r rrrrr r r r 15 14 13 12 11 10 9 8 765432 1 0 EN PWMI Reserved FOLVB FOLVA OLVLB OLVLA OCBE OCAE OPM PWM IEDGB IEDGA EXEDG ECKEN rw rw - rw rw rw rw rwrwrwrwrwrw rw rw 1 |
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