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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STR720 Scheda tecnica(PDF) 357 Page - STMicroelectronics |
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STR720 Scheda tecnica(HTML) 357 Page - STMicroelectronics |
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357 / 401 page  STR720 - MISCELLANEA REGISTERS (GCR - CGC - AHB_ERR) 357/401 CGC Peripheral Clock Gating register 2 (CGC-PCG2) Address: 0xF000_2C0C Reset value: 0x0000 This register configures clock gating for each specific clock signal used by some blocks requiring dedicated clocks for their operations. Each dedicated clock signal is delivered to the related peripheral only when its corresponding gating bit is cleared. Bits 15:3 = Reserved. These bits must be always written to 0. Bits 2:1 = DxCO: Dedicated peripheral x Clock Off 0: Peripheral x dedicated clock is gated off and the block kernel is not clocked. 1: Peripheral x dedicated clock is delivered. Bit 0 = Reserved. This bit must be always written to 0. The following table lists the correspondence between each dedicated peripheral clock and the CGC-PCG2 register bits along with their reset value. 15 14 13 12 11 10 9 8 765432 1 0 Reserved D2CO D1CO Res. -rw rw - Table 77. CGC-PCG2 bit assignment CGC-PCG2 Bit Affected peripheral Reset status D1CO ATAPI-Kernel Off D2CO USB-Kernel Off |
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