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STA450A Scheda tecnica(PDF) 18 Page - STMicroelectronics |
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STA450A Scheda tecnica(HTML) 18 Page - STMicroelectronics |
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18 / 66 page ![]() STA450A 18/66 HOST_SOFTRESET Address : 0x10 Type : W Software Reset : NA Hardware Reset : NA Description When bit 0 of this register is set, a soft reset occurs. The command registers and the interrupt registers are cleared. The STA450A goes into idle mode. HOST_Pllpcm Address : 0x12 Type : R - W Software Reset : NC Hardware Reset : 0x01 Description 00 Not used 01 The PCMCLK pad is in input. This external PCMCLK source is sent to the I2S PCM output. 10 The PCMCLK pad is in output. The internal audio PLL is generating the PCM clock for the I2S PCM output. 11 Same case as 10 but the PCMCLK is in tri-state mode HOST_Plldata Address : 0x11 Type : R/W Software Reset : 0 Hardware Reset : 0 Description Data to be copied in the Level 1 register for system PLL. This register should be used in conjunction with registers HOST_Pllcmd and HOST_Plladd HOST_Pllcmd Address : 0x18 Type : R/W Software Reset : 0 7654 3210 10 7654 3210 12 7654 3210 11 7654 3210 18 |
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