CAT5259 datasheet(5/16 Pages) CATALYST

5 / 16 page

CAT5259

Document No. 2000, Rev. F

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.

POWER UP TIMING (1)(2)

Symbol

Parameter

Max

Units

tPUR

Power-up to Read Operation

tPUW

Power-up to Write Operation

WRITE CYCLE LIMITS

Symbol

Parameter

Max

Units

tWR

Write Cycle Time

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase

cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device

does not respond to its slave address.

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH

Figure 1. Bus Timing

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Reference Test Method

NEND(1)

Endurance

1,000,000

Cycles/Byte

MIL-STD-883, Test Method 1033

TDR(1)

Data Retention

100

Years

MIL-STD-883, Test Method 1008

VZAP(1)

ESD Susceptibility

2000

Volts

MIL-STD-883, Test Method 3015

ILTH(1)

Latch-Up

100

JEDEC Standard 17

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

XDCP TIMING

Symbol

Parameter

Min

Max

Units

tWRPO

Wiper Response Time After Power Supply Stable

µs

tWRL

Wiper Response Time After Instruction Issued

µs

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