3

SCD5031 Rev B

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PWM5031 PWM PIN DESCRIPTION

PIN #

SIGNAL NAME

FUNCTION DESCRIPTION

1

24

VCC

Logic Power

2

50%

Input selects maximum duty cycle (50% or 100%). Logic ''1'' selects 50% max duty

cycle and Output B is the complement of Output A. Logic ''0'' selects 100% and

Output A is in-phase with Output B.

3

SLEEP

This Input shuts down all functions on chip when asserted (Active Hi)

4COMP

stabilize converter.

5

VFB

Negative Input to the error amplifier

6

ISENSE

Input Current sense pin used for current mode control

7SOFT

This High impedance Input is used to limit the error amplifier output voltage. Applying

an RC circuit to this pin provides the standard softstart function. Pull the pin to ground

to force zero duty cycle.

8CSET

Works with Rset to establish oscillator free running frequency. Place cap from this

Input pin to ground. Can synchronize oscillator by overdriving this pin with an external

frequency source.

9RSET

Works with Cset to establish oscillator free running frequency. Place resistor from this

Input pin to ground.

10

PWROK

Logical output of UV lockout circuit -- logic ''1'' indicates chip has valid Vcc

11

VREF

Buffered 3V Output reference voltage

12

VEE

Logic Ground

13

NIN

Auxiliary Op-Amp Inverting Input

14

PIN

Auxiliary Op-Amp Non-Inverting Input

15

AOUT

Auxiliary Op-Amp Output

16

ENAUX

Input Enable of Auxiliary Op-Amp (Active Hi)

17

EN

Logic Input that enables the oscillator and output drivers. Reference voltage remains

valid (Active Hi).

18

19

DRVN

Output stage negative rail

20

OUT B

Totem pole Output B

21

OUTA

Totem pole Output A

22

23

DRVP

Output stage positive rail