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CS7620 Scheda tecnica(PDF) 40 Page - Cirrus Logic |
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CS7620 Scheda tecnica(HTML) 40 Page - Cirrus Logic |
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40 / 70 page ![]() CS7620 40 DS301PP2 4.18 Timing Control - Start of Black Pixels Default = 04h; Read/Write (address 1Ch) 4.19 Timing Control - End of Black Pixels Default = 3Fh; Read/Write (address 1Dh) Bit Number 765432 10 Bit Name Reserved blk_begin3 blk_begin2 blk_begin1 blk_begin0 Default ---- 0100 Bit Mnemonic Function 7:4 - Reserved 3 blk_begin3 Black Pixels: This register indicates the beginning of the black pixels within a horizontal line. Before the black pixels, there can be some extra pixels, due to latency through the horizontal shift register inside the CCD. The default value for this register is 4, since IBM35CCD2PIX1 has 3 extra pixels. (See Figure 28) 2 blk_begin2 1 blk_begin1 0 blk_begin0 Bit Number 765432 10 Bit Name Reserved blk_end6 blk_end5 blk_end4 blk_end3 blk_end2 blk_end1 blk_end0 Default - 0111111 Bit Mnemonic Function 7- Reserved 6 blk_end6 Black Pixels: This register indicates the end of the black pixels within the hor- izontal line. This register is used by the black level loop together with blk_begin, to acquire the proper black level on a line by line basis. Since the loop has some latency, the value stored in this register, should be 10 less than the actual last black pixel in each line. Since in IBM35CCD2PIX1, this number is 73, the default is set to 63. (See Figure 28) 5 blk_end5 4 blk_end4 3 blk_end3 2 blk_end2 1 blk_end1 0 blk_end0 |
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