CS42432 datasheet(47/62 Pages) CIRRUS

47 / 62 page

DS673PP2

7.12

ADC CHANNEL INVERT (ADDRESS 17H)

7.12.1 INVERT SIGNAL POLARITY (INV_AINX)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

7.13

STATUS (ADDRESS 19H) (READ ONLY)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the register

was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register.

Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always

be “0” in this register.

7.13.1 CLOCK ERROR (CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes ac-

tive during the error condition. See “System Clocking” on page 31 for valid clock ratios.

7.13.2 ADC OVERFLOW (ADCX_OVFL)

Default = x

Function:

Indicates that there is an over-range condition anywhere in the CS42432 ADC signal path of each of

the associated ADC’s.

7.14

STATUS MASK (ADDRESS 1AH)

Default = 0000

Function:

The bits of this register serve as a mask for the error sources found in the register “Status (address

654

Reserved

INV_AIN4

INV_AIN3

INV_AIN2

INV_AIN1

654

Reserved

CLK Error

Reserved

ADC2_OVFL

ADC1_OVFL

654

Reserved

CLK Error_M

Reserved

ADC2_OVFL_M ADC1_OVFL_M

CS42432 Scheda tecnica(PDF) 47 Page - Cirrus Logic

CS42432 Scheda tecnica(HTML) 47 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Scheda tecnica Scarica

Link URL