EP9301 datasheet(10/41 Pages) CIRRUS

10 / 41 page

DS636PP5

EP9301

Entry Level ARM9 System-on-Chip Processor

Reset and Power Management

The chip may be reset through the PRSTn pin or through

the open drain common reset pin, RSTOn.

Clocks are managed on a peripheral-by-peripheral basis

and may be turned off to conserve power.

The processor clock is dynamically adjustable from 0 to

166 MHz.

Hardware Debug Interface

The JTAG interface allows use of ARM’s Multi-ICE or

other in-circuit emulators.

12-channel DMA Controller

The DMA module contains 12 separate DMA channels.

Ten of these may be used for peripheral-to-memory or

memory-to-peripheral

access.

Two

these

are

dedicated to memory-to-memory transfers. Each DMA

channel is connected to the 16-bit DMA request bus.

The request bus is a collection of requests, Serial Audio

and

UARTs.

Each

DMA

channel

can

used

independently or dedicated to any request signal. For

each DMA channel, source and destination addressing

can

independently

programmed

increment,

decrement, or stay at the same value. All DMA

addresses are physical, not virtual addresses.

Internal Boot ROM

The Internal 16 kbyte ROM allows booting from FLASH

memory, SPI or UART. Consult the EP93xx User’s

Manual for operational details.

Table N. Reset and Power Management Pin Assignments

Pin Mnemonic

Pin Name - Description

PRSTn

Power On Reset

RSTOn

User Reset In/Out – Open Drain –

Preserves Real Time Clock value

Table O. Hardware Debug Interface

Pin Mnemonic

Pin Name - Description

TCK

JTAG Clock

TDI

JTAG Data In

TDO

JTAG Data Out

TMS

JTAG Test Mode Select

TRSTn

JTAG Port Reset

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