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STM32MP151AAA3 Scheda tecnica(PDF) 53 Page - STMicroelectronics |
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STM32MP151AAA3 Scheda tecnica(HTML) 53 Page - STMicroelectronics |
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53 / 253 page  DS12500 Rev 3 53/253 STM32MP151A/D Functional overview 55 independently on each port. It integrates two transceivers which can be used for either low- speed (1.2 Mbit/s), full-speed (12 Mbit/s) or high-speed operation (480 Mbit/s), the second high-speed transceiver is shared with OTG high-speed. The USB HS is compliant with the USB 2.0 specification. The USB HS controllers require dedicated clocks that are generated by a PLL inside the USB high-speed PHY. 3.45 USB on-the-go high-speed (OTG) The devices embed one USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s) and high-speed operation (480 Mbit/s) shared with USB Host second port. The USB OTG HS is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is generated by a PLL inside RCC or inside the USB high-speed PHY. The main features are: • Combined Rx and Tx FIFO size of 4 Kbyte with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 8 bidirectional endpoints • 16 host channels with periodic OUT support • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (link power management) support • Battery charging specification revision 1.2 support • Internal FS or HS OTG PHY support • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected |
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