AX68002QF datasheet(16/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

1.5 Signal Description

Following abbreviations are used in “Type” column of following pin description tables. Note that some I/O pins

with multiple signal definitions on the same pin may have different attribute in “Type” column for different signal

definition.

Analog Bi-directional I/O

Output, 3.3V with 5V tolerant

Analog Input

Internal Pull-Up (75K)

Analog Output

Internal Pull-Down (75K)

Bi-directional I/O, 3.3V

Power and ground pin

Bi-directional I/O, 3.3V with 5V tolerant

Schmitt Trigger

Input, 3.3V

Tri-state

Input, 3.3V with 5V tolerant

4mA driving strength

Output, 3.3V

8mA driving strength

For example, pin 12 in AX68004 package can be P00 or RXD0. If P00 is selected, its Type is B5/4m/PU; if RXD1

is selected, its Type is I5. In other words, the PU (internal pull-up) only takes effect in P00 signal mode while

RXD1 signal mode doesn’t. User should refer to the table specific to desired function for exact pin type definition.

The multi-function pin settings are configured by Hardware Configuration (HWCFG) in Flash Information Page

Memory. The following abbreviations are used in pin description tables.

Table 1-1: Chip Clock and Reset Pin Description

Chip Clock and Reset

Pin Name

Type

Pin No

Pin Description

100

XIN

12MHz crystal input or oscillator clock input.

This clock is always required for the USB functions and, in most

cases, used as clock reference to the internal 96MHz PLL which

generates 96MHz as main operating system clock.

The recommended reference frequency is 12MHz +/-50ppm, 45 ~

55% clock duty cycle. Note that this input pin is 3.3V tolerant.

XOUT

12MHz crystal output.

RST_N

I5/PU/S 43

Chip Reset input, active low.

RST_N is the hardware reset input used to reset this chip. This input is

AND with internal Power-On-Reset (POR) circuit, which generates the

main system reset for this chip.

SYSCK_SEL

I5/PU

Operating SYStem ClocK frequency SELection input:

0: Select 48MHz operating system clock, please tie to logic low.

1: Select 96MHz operating system clock, please tie to logic high or

NC.

TEST_MODE

I5/PD

Test Mode enable. For normal operation, please always tie to logic low

or NC.

VDDA_PLL

Analog Power for internal 96MHz PLL, 1.8V.

VSSA_PLL

Analog Ground for internal 96MHz PLL.

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