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AM652X Scheda tecnica(PDF) 83 Page - Texas Instruments |
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AM652X Scheda tecnica(HTML) 83 Page - Texas Instruments |
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83 / 277 page  83 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2019, Texas Instruments Incorporated Table 4-47. MMCSD1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC1_CALPAD(1) MMC/SD Calibration Resistor A F23 MMC1_CLK(2)(3)(4) MMC/SD Clock O C27 MMC1_CMD(2)(4) MMC/SD Command IO C28 MMC1_SDCD SD Card Detect (active low) I B24 MMC1_SDWP SD Write Protect I C24 MMC1_DAT0(2)(4) MMC/SD Data IO D28 MMC1_DAT1(2)(4) MMC/SD Data IO E27 MMC1_DAT2(2)(4) MMC/SD Data IO D26 MMC1_DAT3(2)(4) MMC/SD Data IO D27 (1) An external 10kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due to the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus width. Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting. (3) This output signal is also used as a retiming input. It is also recommended to place a 33 Ω resistor in series (close to the processor) to avoid signal reflections. (4) Each of these signals should have an external 50kΩ pull-up resistor connected to the corresponding power supply. 4.3.18 CPTS 4.3.18.1 MAIN Domain Table 4-48. CPTS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CPTS0_RFT_CLK CPTS Reference Clock I D21 CPTS0_TS_COMP CPTS Time Stamp Counter Compare O AF13 CPTS0_TS_SYNC CPTS Time Stamp Counter Bit O AG12 CPTS0_HW1TSPUSH CPTS Hardware Time Stamp Push 1 I B21 CPTS0_HW2TSPUSH CPTS Hardware Time Stamp Push 2 I E21 4.3.19 OLDI 4.3.19.1 MAIN Domain Table 4-49. OLDI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OLDI0_CLKN OLDI Differential Clock (negative) IO L25 OLDI0_CLKP OLDI Differential Clock (positive) IO K25 OLDI0_A0N OLDI Differential Data (negative) IO J28 OLDI0_A0P OLDI Differential Data (positive) IO K28 OLDI0_A1N OLDI Differential Data (negative) IO L27 OLDI0_A1P OLDI Differential Data (positive) IO K27 OLDI0_A2N OLDI Differential Data (negative) IO K24 OLDI0_A2P OLDI Differential Data (positive) IO J24 OLDI0_A3N OLDI Differential Data (negative) IO J26 OLDI0_A3P OLDI Differential Data (positive) IO K26 |
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