TSC51C1 datasheet(21/31 Pages) TEMIC

21 / 31 page

TSC8051C1

Rev. D (14 Jan. 97)

MATRA MHS

Table 7. Status for master transmitter mode.

Status code

Status of I2C bus and SIO1 hardware

08h

A START condition has been transmitted.

10h

A repeated START condition has been

transmitted

18h

SLA+W has been transmitted; ACK has been

received.

20h

SLA+W has been transmitted; NOT ACK has

been received.

28h

Data byte has been transmitted; ACK has been

received.

30h

Data byte has been transmitted; NOT ACK has

been received.

38h

Arbitration lost in SLA+R/W or data bytes.

Table 8. Status for master receiver mode

Status code

Status of I2C bus and SIO1 hardware

08h

A START condition has been transmitted.

10h

A repeated START condition has been

transmitted.

38h

Arbitration lost in NOT ACK bit

40h

SLA+R has been transmitted; ACK has been

received.

48h

SLA+R has been transmitted; NOT ACK has

been received.

50h

Data byte has been received; ACK has been

received.

58h

Data byte has been received; NOT ACK has

been received.

Table 9. Status for miscellaneous states

Status code

Status of I2C bus and SIO1 hardware

00h

Bus error.

F8h

No relevant state information available.

S1DAT contains a byte of serial data to be transmitted or

a byte which has just been received. It is addressable

while it is not in process of shifting a byte. This occurs

when SIO1 is in a defined state and the serial interrupt

flag is set. Data in S1DAT remains stable as long as SI

is set. While data is being shifted out, data on the bus is

simultaneously shifted in; S1DAT always contains the

last byte present on the bus.

S1DAT: Synchronous Serial Data Register

MSB

SFR DAh

LSB

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Symbol

Position

Name and Function

SD0

S1DAT.0

Address bit 0 (R/W) or Data bit 0.

SDX

S1DAT.X

Address bit X or Data bit X.

S1DAT is a read/write register. Its value after reset is

00h.

S1DAT is using TSC8051C1 Special Function Register

address, DAh.

When SIO1 is enabled, P3.6 and P3.7 must be set to 1 to

avoid low level asserting on SCL or SDA lines.

When SIO1 is used, external data memory access is not

available.

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