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DP83261AVF Scheda tecnica(PDF) 71 Page - National Semiconductor (TI) |
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DP83261AVF Scheda tecnica(HTML) 71 Page - National Semiconductor (TI) |
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71 / 132 page  70 Signal Descriptions Interface Organization The BMAC device signals are organized into five Interfaces Control Interface Used for processor access to the BMAC device PHY Interface Interface signals to the DP8325155 PLAYER device MAC Indicate Interface Signals for receiving and processing incoming frames MAC Request Interface Signals used to capture tokens and transmit frames Electrical Interface Signals associated with power supply and clocking Application Note 689 BMAC Device Hardware Design Guide provides a discussion of design considerations and tradeoffs for using the BMAC Device 71 CONTROL INTERFACE The Control Interface operates asynchronous to the operation of the data services During an access the external Control Bus is synchronized with the internal Control Bus The ACK and INT signals are open drain signals to allow wire ORing several such signals Symbol Pin IO Description CBP 10 IO Control Bus Parity Odd parity on CBD7 – 0 CBD7–0 9–6 3–1 I O Control Bus Data 132 CBA7 – 0 131 – 129 I Control Bus Address Address of a particular register 127 – 123 CE 120 I Control Bus Enable Handshake signal used to begin a Control Interface access Active low signal RW 119 I Read EWrite Determines current direction of a Control Interface access ACK 122 OD E Acknowledge Acknowledges that the Control Interface access has been performed Active low open drain signal INT 121 OD E Interrupt Indicates presence of one or more enabled condition(s) from the Event Registers Active low open drain signal 71 |
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