AVDD

IOVDD

SHDNZ

t

1

t

2

t

3

t

4

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PCM1840

SBAS989 – APRIL 2019

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9 Power Supply Recommendations

The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep

the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range.

After all supplies are stable, set the SHDNZ pin high to initialize the device. Assert the SHDNZ pin high only

when all hardware control pins (MSZ, MD0, MD1, FMT0, and FMT1) are driven to the voltage level for the device

desired mode of operation.

on the record data, power down the analog and digital blocks, and put the device into hardware shutdown mode.

Figure 53. Power-Supply Sequencing Requirement Timing Diagram

Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a

power-up event is at least 100 ms.

The PCM1840 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and

an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the

AREG and AVDD pins onboard.