MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1

REV 6

10/95

Dual 4-Stage

Binary Ripple Counter

High–Performance Silicon–Gate CMOS

The MC54/74HC393 is identical in pinout to the LS393. The device inputs

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

This device consists of two independent 4–bit binary ripple counters with

parallel outputs from each counter stage. A

÷ 256 counter can be obtained

by cascading the two binary counters.

Internal flip–flops are triggered by high–to–low transitions of the clock

input. Reset for the counters is asynchronous and active–high. State

changes of the Q outputs do not occur simultaneously because of internal

ripple delays. Therefore, decoded output signals are subject to decoding

spikes and should not be used as clocks or as strobes except when gated

with the Clock of the HC393.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 236 FETs or 59 Equivalent Gates

LOGIC DIAGRAM

Q1

Q2

Q3

Q4

CLOCK

RESET

1, 13

2, 12

3, 11

4, 10

5, 9

6, 8

PIN 14 = VCC

PIN 7 = GND

BINARY

COUNTER

MC54/74HC393

PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Clock

Reset

Outputs

X

H

L

H

L

No Change

L

L

No Change

L

No Change

L

Advance to

Next State

11

12

13

14

8

9

10

5

4

3

2

1

7

6

Q2b

Q1b

RESET b

CLOCK b

VCC

Q4b

Q3b

Q2a

Q1a

RESET a

CLOCK a

GND

Q3a

Q4a

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXD

Ceramic

Plastic

SOIC

1

14

1

14

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

1

14