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97SD3232 Scheda tecnica(PDF) 21 Page - Maxwell Technologies |
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97SD3232 Scheda tecnica(HTML) 21 Page - Maxwell Technologies |
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21 / 39 page ![]() 97SD3232 21 All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM 01.11.05 Rev 2 Write Operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, or 8, like burst read operations. The write start address is specified by the column address and the bank select address (BA0/BA1) at the write command set cycle. 2. Single write: A single write operation is enabled by setting OPCODE ( A9, A8) to (1, 0). In a single write operation, data is only written to the column address and the bank select address (BA0/BA1) specified by the write command set cycle without regard to the burst length setting. ( The latency of data input is 0 clock.) |
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