H5GQ2H24AFR-R0C datasheet(63/172 Pages) HYNIX

Il numero della parte	H5GQ2H24AFR-R0C

Spiegazioni elettronici	2Gb (64Mx32) GDDR5 SGRAM

PDF	172 Pages

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Produttore elettronici	HYNIX [Hynix Semiconductor]

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

4.9 MODE REGISTER 9 (MR9)

Mode Register 9 controls features Pre & De‐Emphasis as shown in Figure 33.

The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=0

and BA3=1.

Figure 33. Mode Register 9 (MR9) Definition

Pre‐Emphasis & De‐Emphasis

The Pre‐Emphasis and De‐Emphasis is enabled by the combination of bit A0 and A1.

The Pre‐Emphasis is on when A1/A0 is 0/1 and the De‐Emphasis is on when A1/A0 is 1/0 or 1/1.

It will be helpful to reduce channel ISI (Inter Symbol Interference) at high speed operation when memory

is in read operation.

BA3 BA2 BA1 BA0

A12

A11

A10

RFU

Pre & De

‐ Emphasis

All Off

Pre‐emphasis

De‐emphasis

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