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AS7C252MPFS18A Scheda tecnica(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C252MPFS18A Scheda tecnica(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 18 page  February 2005 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C252MPFS18A 2/14/05, v.1.3 Alliance Semiconductor 1 of 18 2.5V 2M × 18 pipelined burst synchronous SRAM Features • Organization: 2,097,152 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.1/3.5/3.8 ns •Fast OE access time: 3.1/3.5/3.8 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and global write • Multiple chip enables for easy expansion • 2.5V core power supply • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs Logic block diagram Selection guide -200 -166 -133 Units Minimum cycle time 5 6 7.5 ns Maximum clock frequency 200 166 133 MHz Maximum pipelined clock access time 3.1 3.5 3.8 ns Maximum operating current 450 400 350 mA Maximum standby current 170 150 140 mA Maximum CMOS standby current (DC) 90 90 90 mA Burst logic ADV ADSC ADSP CLK LBO CLK CLR CS 21 19 21 A[20:0] 21 Address D Q CS CLK register 2M x 18 Memory array 18 18 DQb CLK DQ Byte Write registers DQa CLK DQ Byte Write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down DQ[a,b] 2 CE0 CE1 CE2 BWb BWa OE ZZ OE CLK CLK BWE GWE 18 |
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